1. Field of the Invention
The present invention is directed to a memory device and more particularly, to a row decoding circuit applicable to a memory device.
2. Description of Related Art
A memory array in a memory device is composed of a plurality of memory cells. When multiple data is about to be stored in the memory array or the data is to be read from the memory array, the memory device enables corresponding row selecting signals according to memory addresses corresponding to the data to open the memory cells on a corresponding word line. Thus, the data can be stored into or read from the corresponding memory cells. Therefore, in the application of the memory technology, a plurality of row selecting signals is generated by a plurality of row decoders, and a voltage level of each row selecting signal is determined by the row decoder according to the memory address.
Typically, a row decoder is formed by cascoding a plurality of transistors, and sub-threshold leakage, gate direct tunneling leakage and gate induce drain leakage (GIDL) occurring in the transistors would influence the power consumption of the row decoder. Accordingly, how to reduce the leakage of the transistors has become an important subject of designing the row decoders of the memory device.